`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:30:44 12/07/2013
// Design Name:   butterfly
// Module Name:   C:/Users/Jayvee/Desktop/H_264_Decoder/BUTTERFLY_TEST.v
// Project Name:  H_264_Decoder
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: butterfly
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module BUTTERFLY_TEST;

	// Inputs
	reg [15:0] D0;
	reg [15:0] D1;
	reg [15:0] D2;
	reg [15:0] D3;
	reg DCT_or_HDT;
	reg isDirect;
    reg [2:0] cnt;
    reg Clk;
	// Outputs
	wire [15:0] F0;
	wire [15:0] F1;
	wire [15:0] F2;
	wire [15:0] F3;

	// Instantiate the Unit Under Test (UUT)
	butterfly uut (
		.D0(D0), 
		.D1(D1), 
		.D2(D2), 
		.D3(D3), 
		.F0(F0), 
		.F1(F1), 
		.F2(F2), 
		.F3(F3), 
		.DCT_or_HDT(DCT_or_HDT), 
		.isDirect(isDirect)
	);

	initial begin
		// Initialize Inputs
		D0 = 0;
		D1 = 0;
		D2 = 0;
		D3 = 0;
		DCT_or_HDT = 0;
		isDirect = 0;
        cnt = 0;
        Clk = 0;
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
    
    always #20 Clk=~Clk;
    
    always @(posedge Clk) begin
        case(cnt) 
        0:begin
            cnt <= cnt + 1;
            isDirect <= 0;
            DCT_or_HDT <= 0;
            D0 <= 1;
            D1 <= 5;
            D2 <= 9;
            D3 <= 13;
        end
        default:begin
            cnt <= cnt;
        end
        endcase
    end
    
endmodule

